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d a t a sh eet product speci?cation supersedes data of 2000 apr 10 file under integrated circuits, ic19 2001 jun 25 integrated circuits tza3019 2.5 gbits/s dual postamplifier with level detectors and 2 2 switch
2001 jun 25 2 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 features dual postamplifier single 3.3 v power supply wideband operation from 50 khz to 2.5 ghz (typical value) fully differential channels are delay matched on-chip dc-offset compensations without external capacitor interfacing with positive or negative supplied logic switching possibility between channels positive emitter coupled logic (pecl) or current-mode logic (cml) compatible data outputs adjustable from 200 to 800 mv (p-p) single-ended power-down capability for unused outputs and detectors rise and fall times 80 ps (typical value) possibility to invert the output of each channel separately input level-detection circuits for received signal strength indicator (rssi) or loss of signal (los) detection, programmable from 0.4 to 400 mv (p-p) single-ended, with open-drain comparator output for direct interfacing with positive or negative logic reference voltage for output level and los adjustment automatic strongest input signal switch possibility (tza3019 version b) htqfp32 or hbcc32 plastic package with exposed pad. applications postamplifier for synchronous digital hierarchy and synchronous optical network (sdh/sonet) transponder sdh/sonet wavelength converter crosspoint or channel switch pecl driver fibre channel arbitrated loop protection ring monitoring signal level detectors swing converter cml 200 mv (p-p) to pecl 800 mv (p-p) port bypass circuit 2.5 ghz clock amplification. general description the tza3019 is a low gain postamplifier multiplexer with a dual rssi and/or los detector that is designed for use in critical signal path control applications, such as loop-through, redundant channel switching or wavelength division multiplexing (wdm). the signal path is unregistered, so no clock is required for the data inputs. the signal path is fully differential and delay matched. it is capable of operating from 50 khz to 2.5 ghz. the tza3019 htqfp32 and hbcc32 packages can be delivered in three versions: tza3019aht and TZA3019AVH with two rssi signals tza3019bht and tza3019bvh with one rssi and one los signal tza3019cht and tza3019cvh with two los signals. ordering information type number package name description version tza3019aht htqfp32 plastic, heatsink thin quad ?at package; 32 leads; body 5 5 1.0 mm sot547-2 tza3019bht htqfp32 plastic, heatsink thin quad ?at package; 32 leads; body 5 5 1.0 mm sot547-2 tza3019cht htqfp32 plastic, heatsink thin quad ?at package; 32 leads; body 5 5 1.0 mm sot547-2 TZA3019AVH hbcc32 plastic, heatsink bottom chip carrier; 32 terminals; body 5 5 0.65 mm sot560-1 tza3019bvh hbcc32 plastic, heatsink bottom chip carrier; 32 terminals; body 5 5 0.65 mm sot560-1 tza3019cvh hbcc32 plastic, heatsink bottom chip carrier; 32 terminals; body 5 5 0.65 mm sot560-1 tza3019u - bare die; 2.22 2.22 0.28 mm -
2001 jun 25 3 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 block diagram handbook, full pagewidth mgt028 tza3019aht TZA3019AVH offset level a1a 23 a1b out1 24 27 rssi1 25 21 14 v ref 22 out1q offset level a2a 18 a2b out2q 17 level1 12 1 losth1 10 32 4 8 in2q 7 in2 6 5 losth2 11 9 s2 30 inv2 28 level2 13 test 15 inv1 29 s1 31 in1 2 in1q 3 20 16 26 rssi2 19 out2 band gap reference dft switch switch los detector los detector 1 1 v cc1a v cc1a v cc2a v cc2a v cc2b v cc2b v cc1b v cc1b gnd1a gnd2a gnd2b gnd1b fig.1 block diagram (tza3019aht and TZA3019AVH).
2001 jun 25 4 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, full pagewidth mgt027 tza3019bht tza3019bvh offset level a1a 23 a1b out1 24 27 los1 25 21 14 v ref 22 out1q offset level a2a 18 a2b out2q 17 level1 12 1 losth1 10 32 4 8 in2q 7 in2 6 5 losth2 11 9 s2 30 inv2 28 level2 13 test 15 inv1 29 s1 31 in1 2 in1q 3 20 16 26 rssi2 19 out2 band gap reference dft switch switch 5 k w los detector los detector 1 v cc1a v cc1a v cc2a v cc2a v cc2b v cc2b v cc1b v cc1b gnd1a gnd2a gnd2b gnd1b fig.2 block diagram (tza3019bht and tza3019bvh).
2001 jun 25 5 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, full pagewidth mgs553 5 k w tza3019cht tza3019cvh offset level a1a 23 a1b out1 24 27 los1 25 21 14 v ref 22 out1q offset level a2a 18 a2b out2q 17 level1 12 v cc1a v cc1a v cc2a v cc2a v cc2b v cc2b v cc1b v cc1b 1 losth1 10 gnd1a gnd2a gnd2b gnd1b 32 4 8 in2q 7 in2 6 5 losth2 11 9 s2 30 inv2 28 level2 13 test 15 inv1 29 s1 31 in1 2 in1q 3 20 16 26 los2 19 out2 band gap reference dft switch switch 5 k w los detector los detector fig.3 block diagram (tza3019cht and tza3019cvh).
2001 jun 25 6 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 pinning symbol pin pad type (2) description tza3019xht/xvh (1) abc v cc1a 1 1 1 1 s supply voltage for input 1 and los1 circuits in1 2 2 2 2 i differential circuit 1 input; complimentary to pin in1q; dc bias level is set internally at approximately v cc - 0.33 v in1q 3 3 3 3 i differential circuit 1 input; complimentary to pin in1; dc bias level is set internally at approximately v cc - 0.33 v v cc1a 4 4 4 4 s supply voltage for input 1 and los1 circuits n.c. --- 5 - not connected n.c. --- 6 - not connected v cc2a 5 5 5 7 s supply voltage for input 2 and los2 circuits in2 6 6 6 8 i differential circuit 2 input; complimentary to pin in2q; dc bias level is set internally at approximately v cc - 0.33 v in2q 7 7 7 9 i differential circuit 2 input; complimentary to pin in2; dc bias level is set internally at approximately v cc - 0.33 v v cc2a 8 8 8 10 s supply voltage for input 2 and los2 circuits gnd2a 9 9 9 11 s ground for input 2 and los2 circuits losth1 10 10 10 12 i input for level detector programming of input 1 circuit; threshold level is set by connecting external resistors between pins v cc1a and v ref ; when forced to gnd1a or not connected, the los1 circuit will be switched off losth2 11 11 11 13 i input for level detector programming of input 2 circuit; threshold level is set by connecting external resistors between pins v cc2a and v ref ; when forced to gnd2a or not connected, the los2 circuit will be switched off n.c. --- 14 - not connected level1 12 12 12 15 i input for programming output level of output 1 circuit; output level is set by connecting external resistors between pins v cc1a and v ref ; when forced to v cc1a or not connected, pins out1 and out1q will be switched off level2 13 13 13 16 i input for programming output level of output 2 circuit; output level is set by connecting external resistors between pins v cc2a and v ref ; when forced to v cc2a or not connected, pins out2 and out2q will be switched off v ref 14 14 14 17 o reference voltage for level circuit and los threshold programming; typical value is v cc - 1.6 v; no external capacitor allowed n.c. --- 18 - not connected test 15 15 15 19 i for test purposes only; to be left open-circuit in the application gnd2b 16 16 16 20 s ground for output 2 circuit v cc2b 17 17 17 21 s supply voltage for output 2 circuit out2q 18 18 18 22 o pecl or cml compatible differential circuit 2 output; complimentary to pin out2
2001 jun 25 7 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 notes 1. the x in tza3019xht/xvh represents versions a, b and c. 2. pin type abbreviations: o = output, i = input, s = power supply, ttl = logic input and o-drn = open-drain output. out2 19 19 19 23 o pecl or cml compatible differential circuit 2 output; complimentary to pin out2q v cc2b 20 20 20 24 s supply voltage for output 2 circuit n.c. --- 25 - not connected n.c. --- 26 - not connected v cc1b 21 21 21 27 s supply voltage for output 1 circuit out1q 22 22 22 28 o pecl or cml compatible differential circuit 1 output; complimentary to pin out1 out1 23 23 23 29 o pecl or cml compatible differential circuit 1 output; complimentary to pin out1q v cc1b 24 24 24 30 s supply voltage for output 1 circuit gnd1b 25 25 25 31 s ground for output 1 circuit rssi2 26 26 - 32 o output of received signal strength indicator of detector 2 los2 -- 26 33 o-drn output loss of signal detector 2; detection of input 2 signal; direct drive of positive or negative supplied logic via internal 5 k w resistor rssi1 27 -- 34 o output of received signal strength indicator of detector 1 los1 - 27 27 35 o-drn output loss of signal detector 1; detection of input 1 signal; direct drive of positive or negative supplied logic via internal 5 k w resistor inv2 28 28 28 36 ttl input to invert the signal of pins out2 and out2q; directly positive (inverted) or negative supplied logic driven inv1 29 29 29 37 ttl input to invert the signal of pins out1 and out1q; directly of positive (inverted) or negative supplied logic driven s2 30 30 30 38 ttl input selector output 2 circuit; directly positive (inverted) or negative supplied logic driven s1 31 31 31 39 ttl input selector output 1 circuit; directly positive (inverted) or negative supplied logic driven gnd1a 32 32 32 40 s ground for input 1 and los1 circuits gndp pad pad pad - s ground pad (exposed die pad) symbol pin pad type (2) description tza3019xht/xvh (1) abc
2001 jun 25 8 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 fig.4 pin configuration htqfp32 package. handbook, full pagewidth tza3019xht mgs554 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 v cc1a exposed pad v cc2a v cc2a gndp in2q in1q in2 gnd2a losth2 level2 losth1 test rssi2/los2 inv2 gnd1a inv1 out1q rssi1/los1 out1 out2q s1 s2 gnd2b gnd1b out2 v ref level1 v cc1a v cc1b v cc2b v cc2b v cc1b in1 handbook, full pagewidth mgt029 1 323130292827 26 25 24 23 22 21 20 19 18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 in2q in1q in2 losth2 level2 losth1 test rssi2/los2 inv2 inv1 out1q rssi1/los1 out1 out2q s1 s2 out2 v ref level1 in1 tza3019xvh exposed pad v cc1a v cc2a v cc2a gndp gnd2a gnd1a gnd2b gnd1b v cc1a v cc1b v cc2b v cc2b v cc1b fig.5 pin configuration hbcc32 package.
2001 jun 25 9 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 functional description the tza3019 is a dual postamplifier with multiplexer and loss of signal detection (see figs 1, 2 and 3). the rf path starts with the multiplexer, which connects an amplifier to one of the two inputs. it is possible to invert the output for easy layout of the printed-circuit board (pcb). the signal is amplified to a certain level. to guarantee this level with minimum distortion over the temperature range and level range, an active control part is added. the offset compensation circuit following the inverter minimizes the offset. the received signal strength indicator (rssi) or the loss of signal (los) detector uses a 7-stage successive detection circuit. it provides a logarithmic output. the los detector is followed by a comparator with a programmable threshold. the input signal level-detection is implemented to check if the input signal voltage is above the user programmed level. this can insure that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. a second offset compensation circuit minimizes the offset of the logarithmic amplifier. rf input circuit the input circuit contains internal 50 w resistors decoupled to v cc via an internal common mode 12 pf capacitor (see fig.6). the input pins are dc-biased at approximately v cc - 0.33 v by an internal reference generator. the tza3019 can be dc-coupled, but ac-coupling is preferred. in case of dc-coupling, the driving source must operate within the allowable input range (v cc - 1.0vtov cc + 0.3 v). a dc-offset voltage of more than a few millivolts should be avoided, since the internal dc-offset compensation circuit has a limited correction range. when ac-coupling is used, if no dc-compatibility is required, the values of the coupling capacitors must be large enough to pass the lowest input frequency of interest. capacitor tolerance and resistor variation must be included for an accurate calculation. do not use signal frequencies around the low cut-off circuit frequencies (f - 3db(l) = 50 khz for the postamplifiers and f - 3db(l) = 1 mhz for the los circuits). rf output circuit matching the main amplifier outputs (see fig.7) is not mandatory. in most applications, the transmission line receiving end will be properly matched, while very little reflections occur. matching the transmitting end to absorb reflections is only recommended for very sensitive applications. in such cases, pull-up resistors of 100 w should be connected as close as possible to the ic from pins out1 and out1q, and pins out2 and out2q to gnd1b and gnd2b respectively. these matching resistors are not needed in most applications. postampli?er level adjustment the postamplifier boosts the signal up to pecl levels. the output can be either cml- or pecl-level compatible, adjusted by means of the voltage on pins level1 and level2. the dc voltages of pins out1 and out1q, and pins out2 and out2q match with the dc-levels on pins level1 and level2, respectively. due to the receiving end 50 w load resistance, it means that at the same level of v o(p-p) , v level1 and v level2 with ac-coupling are not equal to v level1 and v level2 with dc-coupling (see figs 7 and 8). when pin level1 or level2 is connected to v cc or not connected, the postamplifier is in power-down state (see fig.7). postampli?er dc offset cancellation loop offset control loops connected between the inputs of the buffers a1a and a2a and the outputs of the amplifiers a1b and a2b (see figs 1, 2 and 3) will keep the input of both buffers at their toggle point during the absence of an input signal. the active offset compensation circuit is integrated, so no external capacitor is required. the loop time constant determines the lower cut-off frequency of the amplifier chain. the cut-off frequency of the offset compensations is fixed internally at approximately 5 khz. handbook, halfpage mgs555 420 w 50 w 50 w 12 pf v cc1a, v cc2a in1, in2 in1q, in2q gnd1a, gnd2a fig.6 rf input circuit.
2001 jun 25 10 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, full pagewidth reg 50 w v o 50 w 100 w r1 r2 v level v ref out1, out2 level1, level2 out1q, out2q 100 w mgs556 v cc1a, v cc2a v cc1b, v cc2b v cc v o (v) v level v o(se)(p-p) handbook, full pagewidth mgl811 reg 50 w v o v cc 50 w 100 w r1 r2 v level v ref out1, out2 level1, level2 v cc1a, v cc2a v cc1b, v cc2b out1q, out2q 100 w v o (v) v level v o(se)(p-p) fig.7 rf output configurations. a. dc-coupling. b. ac-coupling. v level = 0.5 v o(se)(p-p) . . level detector in power-down mode: v level1 or v level2 =v cc . v level v ref r1 r1 r2 + ---------------------- = v level = 1.5 v o(se)(p-p) . . level detector in power-down mode: v level1 or v level2 =v cc . v level v ref r1 r1 r2 + ---------------------- =
2001 jun 25 11 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, full pagewidth 0 100 1000 0 200 mgs557 400 600 800 20 40 60 80 v level (% of v ref ) v o(se) (p-p) (mv) dc-coupled ac-coupled fig.8 output signal as a function of v level . ttl logic input of selector and inverter the logic levels are differently defined for positive or negative logic (see fig.9). it should be noted that positive logic levels are inverted if a negative supply voltage is used. outputs as a function of switch input pins s1, s2, inv1 and inv2 see tables 1, 2, 3 and 4. the default value for the switch input pins s1, s2, inv1 and inv2 if not connected, is zero. table 1 out1 and out1q as function of input s1 table 2 out2 and out2q as function of input s2 table 3 out1 and out1q as function of input inv1 table 4 out2 and out2q as function of input inv2 s1 out1 out1q 0 in1 in1q 1 in2 in2q s2 out2 out2q 0 in2 in2q 1 in1 in1q inv1 out1 out1q 0 in1 or in2 in1q or in2q 1 in1q or in2q in1 or in2 inv2 out2 out2q 0 in1 or in2 in1q or in2q 1 in1q or in2q in1 or in2
2001 jun 25 12 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, full pagewidth 1 logic level 0 - 4 - 3 - 2 - 10 (1) v i (v) + 1 + 2 + 3 1.4 v ttl 0.8 v 2.0 v 1.4 v 0.8 v 2.0 v mgs559 v ee v cc gnd handbook, full pagewidth 1 logic level 0 - 10 (1) + 1 + 2 + 3 + 4 v i (v) + 5 + 6 1.4 v ttl 0.8 v 2.0 v 1.4 v 0.8 v 2.0 v mgs560 v cc gnd handbook, full pagewidth 1 logic level 0 - 4 - 3 - 2 - 10 v ee gnd (1) v i (v) + 1 + 2 + 3 1.4 v ttl 0.8 v 2.0 v 1.4 v 0.8 v 2.0 v mgs558 fig.9 logic levels on pins s1, s2, inv1 and inv2 as a function of the input voltages. a. positive circuit supply voltage v cc and positive logic supply voltage v cc . b. negative circuit supply voltage v ee and positive logic supply voltage v cc . c. negative circuit supply voltage v ee and positive logic supply voltage v ee . (1) level not defined.
2001 jun 25 13 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 rssi and los detection the tza3019 allows ac-signal level detection. this can prevent the outputs from reacting to noise during the absence of a valid input signal, and can insure that data only will be transmitted when the signal-to-noise ratio of the input signal is sufficient to insure low bit error rate system operation. the rssi detection circuit uses seven limiting amplifiers in a successive detection topology to closely approximate logarithmic response over a total range of 70 db. the detectors provide full-wave rectification of the ac signals presented at each previous amplifier stage. their outputs are current drivers. each cell incorporates a low-pass filter, being the first step in recovering the average value of the demodulated signal of the input frequency. the summed detector output currents are converted to a voltage by an internal load resistor. this voltage is buffered and available in the a and b versions of the tza3019. when v rssi is used v losth must not be connected to gnd to prevent the los comparator from switching to the standby mode. the los comparator detects an input signal above a fixed threshold, resulting in a low-level at the los circuit output.the threshold level is determined by the voltage on pins losth1 or losth2 (see fig.10). a filter with a time constant of 1 m s nominal is included to prevent noise spikes from triggering the level detector. the comparator (with internal 3 db hysteresis) drives an open-drain circuit with an internal resistor (5 k w ) for direct interfacing to positive or negative logic (see fig.11). only available in the b and c versions of the tza3019. the response is independent of the sign of the input signal because of the particular way the circuit has been built. this is part of the demodulating nature of the detector, which results in an alternating input voltage being transformed to a rectified and filtered quasi dc-output signal. for the tza3019 the logarithmic voltage slope is j = 1/12.5 db/mv and is essentially temperature and supply independent through four feedback loops in the reference circuit. the internal los detector output voltage is based on v ref . the demodulator characteristic depends on the waveform and the response depends roughly on the input signal rms value. this influences high frequencies, a square wave input of 2.4 ghz (los circuit bandwidth of 2.4 ghz) offsets the intercept voltage by 20%. v losth can be calculated using the following formula: v losth =v rssi = (1) where s rssi = sensitivity (see chapter characteristics). example: a 200 mv (p-p) single-ended 1.2 gb/s prbs signal has an v rssi of v cc - 1.013 v. a full understanding of the offset control loop is useful. the primary purpose of the loop is to extend the lower end of the dynamic range in any case where the offset voltage of the first stage might be high enough to cause later stages to prematurely enter limiting, caused by the high dc-gain of the amplifier system. the offset is automatically and continuously compensated via a feedback path from the last stage. an offset at the output of the logarithmic converter is equivalent to a change of amplitude at the input. consequently, with dc-coupling, signal absence, either low-level or high-level is detected as a full signal, only signals with an average value equal to zero give zero output. version b can be used for an auto function, which switches the strongest input signal to output 1 and the weakest to output 2. to achieve this output v rssi2 must be used as the reference voltage for input v losth . then the output los1 can switch s1 and s2. v cc 0.458 s rssi 20 log v i(p-p) 26e 8 C ------------------- - ? ?? C + n dbook, halfpage 70 30 los1, los2 low-level los1, los2 high-level 50 v cc - 0.8 v cc - 0.48 v cc - 1.12 60 20 40 10 3 10 2 10 1 10 - 1 mgs564 v losth1 , v losth2 (% of v ref ) v rssi1 , v rssi2 (v) v i(se) (p-p) (mv) (1) (3) (2) 10 v cc - 0.16 fig.10 loss of signal assert level. (1) prbs pattern input signal with a frequency <1 ghz. (2) linearity error typically 0.5 db. (3) j = 1/12.5 db/mv.
2001 jun 25 14 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, halfpage mgs563 gnd 56 k w v cc i los los1, los2 gnd1a, gnd2a 5 k w tza3019 handbook, halfpage mgs561 v ee i los gnd los1, los2 gnd1a, gnd2a 5 k w 56 k w tza3019 fig.11 loss of signal output pins los1 and los2. v cc - v ee <7v. b. negative supply and positive logic. c. negative supply and negative logic. a. positive supply and positive logic. handbook, halfpage mgs562 v cc 5.6 k w v ee i los gnd los1, los2 gnd1a, gnd2a 5 k w tza3019 supply current for the supply currents i cc1b and i cc2b , see fig.0. using a positive supply voltage although the tza3019 has been designed to use a single + 3.3 v supply voltage (see fig.13), some care should be taken with respect to rf transmission lines. the on-chip signals refer to the various v cc pins. the external transmission lines will most likely be referred to the pins v gnd1a , v gnd2a , v gnd1b and v gnd2b , being the system ground. the rf signals will change from one reference plane to another when interfacing the rf inputs and outputs. a positive supply application is very vulnerable to interference with respect to this point. for a successful +3.3 v application, special care should be taken when designing the pcb layout in order to reduce the influence of interference and to keep the positive supply voltage as clean as possible. mgs566 0 0.5 1 v o(se) (p-p) (v) 0 0.8 0.2 40 60 i cc1b, i cc2b (ma) (1) 5 17 58 50 20 10 30 (1) i cc1b and i cc2b at t amb =25 c. fig.0 supply current as a function of output voltage.
2001 jun 25 15 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 limiting values in accordance with the absolute maximum rating system (iec 60134). thermal characteristics notes 1. jedec standard. 2. htqfp32 and hbcc32 packages. symbol parameter min. max. unit v cc supply voltage - 0.5 +5.5 v v n dc voltage pins in1, in1q, in2, in2q, losth1, losth2, level1, level2, v ref , test, out2q, out2, out1q, out1, gndp, v cc1a ,v cc2a , v cc1b and v cc2b - 0.5 v cc + 0.5 v pins los1, los2, inv1, inv2, s1 and s2 - 0.5 +7 v i n dc current pins in1, in1q, in2 and in2q - 20 +20 ma pins losth1, losth2, level1 and level2 0 14 m a pins v ref, test, los1 and los2 - 1+1ma pins out1, out1q, out2 and out2q - 30 +30 ma pins inv1, inv2, s1 and s2 0 20 m a p tot total power dissipation - 1.2 w t stg storage temperature - 65 +150 c t j junction temperature - 150 c t amb ambient temperature - 40 +85 c symbol parameter conditions value unit r th(j-s) thermal resistance from junction to solder point (exposed die pad) note 1 15 k/w r th(j-a) thermal resistance from junction to ambient 1s2p multi-layer test board; notes 1 and 2 33 k/w r th(s-a) thermal resistance from solder point to ambient (exposed die pad) 1s2p multi-layer test board; notes 1 and 2 18 k/w r th(s-a)(req) required thermal resistance from solder point to ambient los circuits switched on v o = 200 mv (p-p) single-ended; both output circuits 60 k/w v o = 800 mv (p-p) single-ended; both output circuits 30 k/w
2001 jun 25 16 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 characteristics typical values at t amb =25 c and v cc = 3.3 v; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages referenced to ground; note 1; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply s upply pins v cc1a ,v cc1b ,v cc2a and v cc2b v cc supply voltage 3.13 3.3 3.47 v i cc1a , i cc2a supply current a los circuit power-down 14 24 34 ma los circuit switched on 24 40 56 ma i cc1b , i cc2b supply current b ampli?er power-down 2 6 10 ma v o = 200 mv (p-p) single-ended; one output circuit 11 17 24 ma v o = 800 mv (p-p) single-ended; one output circuit 43 60 77 ma p tot total power dissipation power-down 100 200 300 mw both los circuits switched on v o = 200 mv (p-p) single-ended; both output circuits 220 380 555 mw v o = 800 mv (p-p) single-ended; both output circuits 450 660 925 mw tc temperature coef?cient los circuit switched on; i cc1a ; i cc2a - 80 - 50 - 30 m a/k v o = 800 mv (p-p) single-ended; i cc1b ; i cc2b - 50 - 30 - 15 m a/k t j junction temperature - 40 - +125 c t amb ambient temperature - 40 +25 +85 c inputs multiplexer and loss of signal detector pecl or cml input pins in1, in1q, in2 and in2q v i(p-p) input voltage swing (peak-to-peak value) single-ended; notes 2 and 3 50 - 500 mv v i(bias) dc input bias voltage v cc - 0.4 v cc - 0.33 v cc - 0.28 v v i dc and ac input window voltage note 3 v cc - 1.0 - v cc + 0.3 v r i input resistance single-ended 35 50 70 w c i input capacitance single-ended; note 3 0.6 0.8 1.2 pf
2001 jun 25 17 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 postampli?er a mplifiers a1a, a1b, a2a and a2b g v small signal voltage gain v o = 200 mv (p-p) single-ended; note 4 9 1520db v o = 800 mv (p-p) single-ended; note 4 21 29 34 db f d signal path data rate notes 5 and 9 - 2.5 - gbits/s f - 3db(l) low - 3 db cut-off frequency dc compensation note 3 2 5 10 khz f - 3db(h) high - 3 db cut-off frequency - 2.0 - ghz t pd propagation delay note 3 150 200 250 ps d t pd propagation delay difference at the same signal levels; note 3 - 05ps j total jitter 20 bits of the 28.5 kbits pattern; notes 3 and 6 - 8 - ps a ct crosstalk crosstalk of ic only - 110 - db pecl or cml output pins out1, out1q, out2 and out2q v o(se)(p-p) single-ended output voltage (peak-to-peak value) 50 w load 200 - 800 mv tc temperature coef?cient output level - 1 0 +1 mv/k t r rise time 20% to 80%; notes 5 and 6 - 80 - ps t f fall time 80% to 20%; notes 5 and 6 - 80 - ps r o output resistance single-ended 70 100 130 w c o output capacitance single-ended; note 3 0.6 0.8 1.2 pf l evel control input pins level1 and level2 v i input voltage v cc - v ref - v cc v r i input resistance measured to v cc1a or v cc2a 150 350 600 k w multiplexer and inverter switch pecl or cml input pins in1, in1q, in2 and in2q a os(red) input offset reduction v o = 200 mv (p-p) single-ended; note 7 3.8 9 13.5 db v o = 800 mv (p-p) single-ended; note 7 6 1422db v io(cor) input offset voltage correction range peak-to-peak value; single-ended - 10 - +10 mv v n(i)(eq)(rms) equivalent input noise voltage (rms value) v o = 800 mv (p-p) single-ended; note 3 - 75 170 m v fn noise factor note 3 - 512db symbol parameter conditions min. typ. max. unit
2001 jun 25 18 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 s witch circuit t a assert time multiplexer and inverter - 100 - ns t d de-assert time multiplexer and inverter - 80 - ns ttl input pins s1, s2, inv1 and inv2 v il low-level input voltage positive logic; note 10 - 0.3 - +0.8 v v ih high-level input voltage positive logic; note 10 2.0 - v cc + 0.8 v r i input resistance measured to gnd1a or gnd2a 100 180 400 k w i i input current - 40 - +40 m a received signal strength indicator and loss of signal detector rssi and los circuit v i(se)(p-p) single-ended input voltage swing (peak-to-peak value) 0.4 - 400 mv dr dynamic range 57 60 63 db s rssi los sensitivity 50 mhz, square; note 8 10 12.5 15 mv/db 620 mhz, square; note 8 10 12 14 mv/db 1.2 ghz, square; note 8 9 11 13.5 mv/db 100 mb/s prbs (2 31 - 1); note 8 9 12.5 15 mv/db 1.2 gb/s prbs (2 31 - 1); note 8 10 12 14.5 mv/db 2.4 gb/s prbs (2 31 - 1); note 8 10 12 14 mv/db tc sens temperature coef?cient sensitivity - 20 + 2 m v/dbk le linearity error see fig.10; note 3 - 0.5 1 db a os(red) input offset reduction notes 3 and 7 25 35 50 db v io(cor) on-chip dc-offset compensation correction range peak-to-peak value single-ended - 5 - +5 mv f - 3db(l) low - 3 db cut-off frequency 0.5 1 2 mhz f - 3db(h) high - 3 db cut-off frequency note 8 1.5 2 2.5 ghz los circuit hys los los hysteresis input signal waveform dependency 2.0 3.0 4.0 db t a assert time note 3 -- 5 m s t d de-assert time note 3 -- 5 m s symbol parameter conditions min. typ. max. unit
2001 jun 25 19 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 notes 1. it is assumed that both cml inputs carry a complementary signal with the specified peak-to-peak value (true differential excitation). 2. minimum signal with limiting output. 3. guaranteed by design. 4. g v = 5. based on - 3db cut-off frequency. 6. v i = 100 mv (p-p) single-ended and v o = 200 mv (p-p) single-ended. 7. input offset reduction = 8. sensitivity depends on the waveform and is therefore a function of - 3 db cut-off frequency see equation (1). 9. low limit can go as low as dc if input signal overrides input offset voltage correction range. 10. when using a negative supply voltage, positive or negative logic can be used. the values will be different (see fig.9). i nput pins losth1 and losth2 v i input voltage 0 - v cc v r i input resistance measured to gnd1a or gnd2a 150 350 600 k w o utput pins los1 and los2 i o(sink) output sink current -- 1ma r o output resistance internal output series resistance 3.5 5 6.5 k w o utput pins rssi1 and rssi2 v o output voltage v cc - 1.2 - v cc v i o output current - 1 - +1 ma band gap reference circuit o utput pin v ref v ref reference voltage v cc - 1.85 v cc - 1.6 v cc - 1.45 v c ext allowed external capacitance -- 10 pf i o(sink) output sink current -- 500 m a symbol parameter conditions min. typ. max. unit v o v i ------ g ac g dc -----------
2001 jun 25 20 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 application information rf input and output connections striplines, or microstrips, with an odd mode characteristic impedance of z o =50 w have to be used for the differential rf connections on the pcb. this applies to both the signal inputs and the signal outputs. the two lines in each pair should have the same length. grounding and power supply decoupling the ground connection on the pcb needs to be a large copper filled area connected to a common ground plane with an inductance as low as possible. to minimize low frequency switching noise in the vicinity of the tza3019, the power supply line should be filtered once using a beaded capacitor circuit with a low cut-off frequency. the exposed die pad gndp connection on the pcb also needs to be a large copper area to improve heat transfer to the pcb and thus support ic cooling (see figs 13 and 14).
2001 jun 25 21 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, full pagewidth in1 in1q in2 in2q out2 out2q v cc1b v cc1b v cc2b v cc2b v cc1a v cc1a v cc2a v cc2a out1 out1q los2 level2 s2 gnd1a losth1 s1 inv2 inv1 losth2 gnd1b gnd2b gnd2a los1 0603 htqfp 0603 0603 0603 0603 0603 0603 012345mm 0603 0603 0603 0603 level1 v ref test 0603 0603 0603 0603 0603 0603 0603 0603 signal/gndp gnd v cc v cc boundary of 200 mm 2 area to central gnd decoupling to central gnd decoupling to central gnd decoupling to central gnd decoupling 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 mgs568 fig.13 pcb layout for positive supply voltage. in order to enable heat flow out of the package, the following measures have to be taken: (1) solder the 3 3 mm 2 die pad to a plane with maximum size. (2) add a plane with minimum 200 mm 2 in an inner layer, surrounded by ground layers. (3) use maximum amount of vias to connect two planes. (4) use minimum of openings in heat transport area between hot plane and ground planes.
2001 jun 25 22 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, full pagewidth in1 in1q in2 in2q out2 out2q out1 out1q los2 level2 s2 losth1 s1 inv2 inv1 losth2 los1 0603 0603 0603 0603 0603 0603 0603 012345mm 0603 0603 0603 0603 level1 v ref test 0603 0603 0603 0603 0603 0603 0603 0603 boundary of 200 mm 2 area to central gnd decoupling to central gnd decoupling to central gnd decoupling to central gnd decoupling 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 mgs567 htqfp v cc1b v cc1b v cc2b v cc2b v cc1a v cc1a v cc2a v cc2a gnd1a gnd1b gnd2b gnd2a signal/gndp gnd v cc v cc fig.14 pcb layout for negative supply voltage. in order to enable heat flow out of the package, the following measures have to be taken: (1) solder the 3 3 mm 2 die pad to a plane with maximum size. (2) add a plane with minimum 200 mm 2 in an inner layer, surrounded by ground layers. (3) use maximum amount of vias to connect two planes. (4) use minimum of openings in heat transport area between hot plane and ground planes.
2001 jun 25 23 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 bonding pad locations note 1. all x and y coordinates represent the position of the centre of the pad in m m with respect to the centre of the die (see fig.15). symbol pad coordinates (1) xy v cc1a 1 - 928 +710 in1 2 - 928 +553 in1q 3 - 928 +396 v cc1a 4 - 928 +239 n.c. 5 - 928 +81 n.c. 6 - 928 - 81 v cc2a 7 - 928 - 239 in2 8 - 928 - 396 in2q 9 - 928 - 553 v cc2a 10 - 928 - 710 gnd2a 11 - 707 - 928 losth1 12 - 550 - 928 losth2 13 - 393 - 928 n.c. 14 - 236 - 928 level1 15 - 79 - 928 level2 16 +79 - 928 v ref 17 +236 - 928 n.c. 18 +393 - 928 test 19 +550 - 928 gnd2b 20 +707 - 928 v cc2b 21 +928 - 710 out2q 22 +928 - 553 out2 23 +928 - 396 v cc2b 24 +928 - 239 n.c. 25 +928 - 81 n.c. 26 +928 +81 v cc1b 27 +928 +239 out1q 28 +928 +396 out1 29 +928 +553 v cc1b 30 +928 +710 gnd1b 31 +707 +928 rssi2 32 +550 +928 los2 33 +393 +928 rssi1 34 +236 +928 los1 35 +79 +928 inv2 36 - 79 +928 inv1 37 - 236 +928 s2 38 - 393 +928 s1 39 - 550 +928 gnd1a 40 - 707 +928 symbol pad coordinates (1) xy
2001 jun 25 24 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 handbook, full pagewidth tza3019u x y 0 0 mgt030 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 in2q in1q in2 losth2 level2 losth1 n.c. test rssi2 inv2 inv1 los2 rssi1 los1 s1 s2 out1q out1 out2q n.c. n.c. out2 v ref level1 n.c. n.c. n.c. in1 v cc1a v cc2a v cc2a gnd2a gnd1a gnd2b gnd1b v cc1a v cc1b v cc2b v cc2b v cc1b fig.15 bonding pad locations tza3019u.
2001 jun 25 25 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 package outlines unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v q references outline version european projection issue date iec jedec eiaj mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 5.1 4.9 0.5 7.1 6.9 0.89 0.61 7 0 0.08 0.08 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot547-2 99-06-15 d (1) e (1) 5.1 4.9 7.1 6.9 d h e h 3.1 2.7 3.1 2.7 0.89 0.61 b p e q e a 1 a l p detail x l b 8 1 32 25 d h b p e h a 2 v m b d z d a c z e e v m a x 17 24 16 9 y w m w m 0 2.5 5 mm scale htqfp32: plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm sot547-2 d h e h heathsink side (a ) 3 pin 1 index
2001 jun 25 26 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 4.2 a 1 b a 2 unit d e 1 e 1 references outline version european projection issue date 99-09-10 00-02-01 iec jedec eiaj mm 0.80 0.10 0.05 0.70 0.60 5.1 4.9 3.2 3.0 5.1 4.9 3.2 3.0 0.35 0.20 dimensions (mm are the original dimensions) sot560-1 mo-217 d 1 0.50 0.30 b 1 0.50 0.35 b 2 0.50 0.35 b 3 4.15 e 3 e 0.5 w e xy 0.15 0.15 0.05 4.2 e 2 4.15 e 4 0.2 v 0 2.5 5 mm scale sot560-1 hbcc32: plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm a max. detail x y va e e 1 e 3 d 1 e 2 x d e a b c 32 1 e 4 e 1 a 1 a 2 a x c x b w m w m w m w m b 2 b b 3 b 1 ball a1 index area
2001 jun 25 27 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2001 jun 25 28 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. package soldering method wave reflow (1) bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a.
2001 jun 25 29 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. bare die ? all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used.
2001 jun 25 30 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 notes
2001 jun 25 31 philips semiconductors product speci?cation 2.5 gbits/s dual postampli?er with level detectors and 2 2 switch tza3019 notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2001 72 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 7 - 9 rue du mont valrien, bp317, 92156 suresnes cedex, tel. +33 1 4728 6600, fax. +33 1 4728 6638 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: philips hungary ltd., h-1119 budapest, fehervari ut 84/a, tel: +36 1 382 1700, fax: +36 1 382 1800 india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 403510/200/02/pp 32 date of release: 2001 jun 25 document order number: 9397 750 08204

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